A MICROFABRICATION TECHNOLOGY LIBRARY

Self-Aligning Polysilicon Gate MOSFETTechnology Description & Documentation

Mike Sorenson & Justin Jackson - GraduateStudents, ECEDepartment

Special Thanks to Divesh Kapoor for web-pageoutline, format, and teaching tutorials.

Introduction

The thought of placing several electronicdevices on a single substrate was first considered in the late 1950s. In 40years, the technology has evolved from making simple chips containing a fewcomponents to fabrication of microprocessors that use close to 50 milliontransistors as well as memories that accommodate more than 1 billiontransistors. This web-page provides constructs for more advanced chipmanufacturing capabilities and processes with the use of self-aligningPolysilicon technology, which is available for use at the University of Utah MicrofabricationLaboratory.

The details of the process,documentation, equipment & supplies necessary are listed below. Measurementsand pictures of completed devices can be accessed here. The mask set designedfor this technology is linked below for reference. This webpage is suitable forresearch students from other departments/schools who intend to use theSelf-Aligning Polysilicon Gate MOSFET process at the Microfabrication facility.

Self-Aligning Polysilicon Gate MOSFETTechnology Details

The work starts with laying out thedevices to be fabricated, using Cadence Virtuoso, a CAD tool available forstudents at the CADE Computer Laboratory, in Room 224 of Building EMCB. Aftercompleting the layout, it has to be extracted to a .gds file. The .gds file hasto be converted to a .em file, which is used by the pattern generator togenerate the reticles. This conversion is done using a program, accessible on acomputer in the research lab-room in the Microfabrication Laboratory. Thereticles generated by the pattern generator can be stepped & repeated tocreate the mask set for the 4-step MOSFET process. This mask set is used tofabricate the devices, using the process steps. After completing the process,the fabricated devices must be tested. Process steps can be added or removeddepending on the individual requirements. Detailed description of each step, islisted below:

  1. Self-Aligning Polysilicon Gate MOSFET: Technology Description, Polysilicon Recipe for Canary Furnaces

  2. Devices

  3. Teaching Manuals

  4. Self-Aligning Polysilicon Gate MOSFET Process: Process Steps

  5. Measurements and Pictures of fabricated devices

  6. CAD Files: Layout Library, .gds map file

Equipment and Supplies

All the needs of any project using theSelf-Aligning Polysilicon Gate MOSFET process can be satisfied by the facilitiesavailable at the MicrofabricationLaboratory. The project requirements are:

The time frame for any project usingthis process is around 4 to 6 weeks.

Technology Road Map

In addition to the four existing steps, morelayers will be added. In the near future, we should see the addition of a BiCMOSPolysilicon process and a second metal layer to the single nMOSFET processlisted above. With the implementation of a BiCMOS Polysilicon process, thistechnology will be able to produce standard cell devices with complementarytransistors. Once a second metal layer process is available, more complicatedcircuits can be implemented, in which the first metal layer can be used forlocal interconnections and the second metal layer can be used for globalrouting. These additional technologies will allow for highly complexcircuitry consisting of up to 20,000 transistors.