The thought of placing several electronic devices on a single substrate was first considered in the late 1950s. In 40 years, the technology has evolved from making simple chips containing a few components to fabrication of microprocessors that use close to 50 million transistors as well as memories that accommodate more than 1 billion transistors. One of many such technologies, the Metal Gate BiCMOS process, is available for use at the University of Utah Microfabrication Laboratory.
The details of the process, documentation, teaching manuals, equipment & supplies needs, measurement and pictures cane be accessed here. A mask set along with the teaching manual appropriate for ECE/MSE 5201 course, the introductory microelectronics class is also avaialble. The manuals are also suitable for research students from other departments/schools who intend to use the Metal Gate BiCMOS process at the Microfabrication facility.
The work starts with laying out the devices to be fabricated, using Cadence Virtuoso, a CAD tool available for students at the Cade Computer Laboratory, in Room 224, EMCB. After completing the layout, it has to be extracted to a .gds file. The .gds file has to be converted to a .em file, which is used by the pattern generator to generate the reticles. This conversion is done using a program, accessible on a computer in the research lab-room in the Microfabrication Laboratory. The reticles generated by the pattern generator can be stepped & repeated to create the mask set for the 5-step BiCMOS process. This mask set is used to fabricate the devices, using the process steps. After completing the process, the fabricated devices must be tested. Process steps can be added or removed depending on the individual requirements. Detailed description of each step, is listed below:
All the needs of any project using Metal Gate BiCMOS process can be satisfied by facilities available at the Microfabrication Laboratory. The project requirements are:
The time frame for any project using this process is around 4 to 6 weeks.
In addition to the five existing steps, more layers can be added. In the next year, we should see addition of the polysilicon layer and a second metal layer to the BiCMOS process. With a polysilicon gate instead of metal gate, the process will become self aligned, since diffusion/ion-implantation will be after the gate oxide growth and polysilicon deposition, which will result in the increase of the yield. Once second metal layer is process is available, more complicated circuits can be implemented, in which metal 1 layer can be used for local interconnections and second metal layer can be used for global routing.